Due to the decreasing feature size of CMOS transistors, more and more signal processing is being transferred from the analogue domain to the digital domain. Also, high levels of integration have enabled complete systems to be integrated on a single-chip, including both analogue and digital processing, and commonly referred to as System On Chip (SOC). However, although CMOS provides improved transistor performance for digital processing, the performance of CMOS for analogue processing is limited. Some of the problems associated with analogue subsystems are process, voltage and temperature (PVT) variations, non-ideal transistor characteristics such as low-gain, and limited voltage headroom due to lower supply voltages. A large part of a system cost, in terms of power consumption and chip area, is due to addressing these problems in the analogue subsystem of a SOC. This situation can be improved if the traditional analogue designs are combined with digital circuits for calibrating out the imperfections that are present in an analogue circuit, enabling the analogue sub-system requirements to be relaxed and overall system cost to be reduced.
A scheme for the calibration of analogue circuits in a radio transceiver is disclosed in U.S. Pat. No. 7,181,205 B1. In that scheme, amplitude and phase errors of modulation and demodulation in a transceiver are corrected by a self calibration procedure in which a test signal is applied to the baseband input of the transmitter, and the output of the modulator is looped back to the input of the demodulator. The amplitude and phase errors of the resulting signal at the baseband output of the receiver are detected, and the contributions of the transmitter and receiver to the errors are separated and resolved into amplitude and phase components. Adjustments are then made to the amplitude and phase balance in the transmit and receive signal paths to correct the errors.
The present invention seeks to provide improvements in calibration.